Assertion Check

SystemVerilog
, ,
8

In reply to rkg_:
You are missing the [*6], also using both |=> ##1, and missing the o_fll_lock de assertion if needed

 
property p_unlock_condition_check_unlock_prog_00; 
        int inc_count, dec_count;
 @(posedge sampled_monclk) disable iff (!i_en_fll)
   ( $rose (o_fll_lock) && i_fll_unlock_prog == 2'b00, inc_count=0, dec_count=0) |-> 
            ##1 (1, inc_count+= (o_fll_inc==1),dec_count+= (fll_dec==1))[*6] ##0 
            !o_fll_lock==(inc_count==4 || dec_count==4) 
     ##0 !o_fll_lock; // if needed 
endproperty
// note the " |-> ##1 (expr1)[*6] ##0..." 
// this is different from 
// " |-> (##1 (expr1))[*6] ##0.."
//

Ben systemverilog.us