In reply to ben@SystemVerilog.us:
I am writing assertion to check the o_fll_lock deassertion.
Specification :- At posedge of o_fll_lock happen , four consecutive of o_fll_inc signal or fll_dec signal detected , o_fll_lock should be de-asserted.
property p_unlock_condition_check_unlock_prog_00;
int inc_count, dec_count;
@(posedge sampled_monclk) disable iff (!i_en_fll)
( $rose (o_fll_lock) && i_fll_unlock_prog == 2'b00, inc_count=0, dec_count=0) |=>
(##1 (1, inc_count+= (o_fll_inc==1),dec_count+= (fll_dec==1)))##0
!o_fll_lock==(inc_count==4 || dec_count==4);
endproperty
Problem :- assertion is getting finished before the o_fll_lock de assertion.
Could someone help, what mistake i am doing and how can i print the value of inc_count in my log ?