In reply to ben@SystemVerilog.us:
Hi Ben ,
below line is causing problem
( $rose (o_fll_sar_eoc) , i_fll_unlock_prog == 2’b00, inc_count=0, dec_count=0)
am i doing anything wrong here
case - 1 → is fine
property p_incdec;
int inc_count, dec_count;
@(posedge sampled_monclk) disable iff (!i_en_fll)
( $rose (o_fll_sar_eoc) , inc_count=0, dec_count=0) |->
(##1 (1, inc_count+= $rose(o_fll_inc),dec_count+= $rose(fll_dec)))[*6] ##0
o_fll_lock==(inc_count==2 || dec_count==2);
endproperty
case-2 --is fine
property p_incdec;
int inc_count, dec_count;
@(posedge sampled_monclk) disable iff (!i_en_fll)
( i_fll_unlock_prog == 2'b00, inc_count=0, dec_count=0) |->
(##1 (1, inc_count+= $rose(o_fll_inc),dec_count+= $rose(fll_dec)))[*6] ##0
o_fll_lock==(inc_count==2 || dec_count==2);
endproperty
case-3 → getting compilation error
property p_incdec;
int inc_count, dec_count;
@(posedge sampled_monclk) disable iff (!i_en_fll)
( $rose (o_fll_sar_eoc) , i_fll_unlock_prog == 2'b00, inc_count=0, dec_count=0) |->
(##1 (1, inc_count+= $rose(o_fll_inc),dec_count+= $rose(fll_dec)))[*6] ##0
o_fll_lock==(inc_count==2 || dec_count==2);
endproperty
do we have limitation number of expression on antecedent ?