Assertion Check

SystemVerilog
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4

In reply to rkg_:
On Q1: You could use a casestatement. However, that really does not simplify things as it makes the assertion more complex, harder to read, and harder to debug. I prefer to have 4 separate assertions; when an error occurs, you would know immediately which of the 4 cases causes the error. The general guidelines on assertions is to write more of smaller assertions than less of complex ones.

On Q2:


bit lock; 
always_ff @(posedge sampled_monclk) begin
    if($rose (o_prog_out_fll[0])) lock <= 1'b1;     
end


property sar_eoc_assertion_check_prpty ;
	@(posedge sampled_monclk ) disable iff (!i_en_fll)
	$rose (o_prog_out_fll[0])&& !lock && i_en_sar  |=> $rose (o_fll_sar_eoc); 
endproperty