In reply to ben@SystemVerilog.us:
Hi Ben
Thanks you.
I don’t understand your need for the case → i have to write the assertion to check the lock condition ( which you gave me solution above) where a can have 4 value (00, 01, 10,11) based on value of a, number of cycle (between 1 to 6 clock cycle of ref_clk) will change like for 00 it is (1 to 6) and for 01 it is (1 to 8) like so on.
One more doubts :
I have written property below
property sar_eoc_assertion_check_prpty ;
@(posedge sampled_monclk ) disable iff (!i_en_fll)
$rose (o_prog_out_fll[0])&& i_en_sar |=> $rose (o_fll_sar_eoc);
endproperty
I want to put constraint on o_prog_out_fll [0] so it should only trigger the assertion at first transition on prog_out_fll (0 → 1) so that property should not trigger again when pro_out_fll goes from 0 to 1
is it possible ?