Assertion Check

SystemVerilog
, ,
26

In reply to ben@SystemVerilog.us:
Hi Ben,

Thanks for suggestion and i am totally agree with you.

Just one doubt on below assertion

property p_lock_condition_check_unlock_prog_01; 
         @(posedge sampled_monclk) disable iff (!i_en_fll)
      ( (o_fll_sar_eoc == 1) && i_fll_unlock_prog == 2'b01 )   |-> 
            ##1 (($rose(o_fll_inc)[=2] or $rose(fll_dec)[=2]) intersect 1'b1[*1:8])
            ##0 o_fll_lock;
    endproperty

** intersect 1’b1[*1:8] , will it start matching just after sar_eoc==1. is it correct understanding ?

** if yes, how to put condition so that it should only match after first posedge of fll_inc and fll_dec (anytime after sar_eoc==1)