Assertion :- check the signal is asserted whenever count value exceed to 64

SystemVerilog
,
9

In reply to rkg_:

 $past(expr1     [, number_of_ticks]     [, expr2] [,clk_evnt])
// needed to add the clocking event in $past
initial begin 
  repeat(2) @(posedge i_mon_clk); // startup for $past, need 1 clk min  
  forever begin : fvr
    @(posedge i_mon_clk);
    if ((i_ref_clk) == $past(i_ref_clk, 1,,@(posedge i_mon_clk)) ) ref_clk_toggling<=1'b0;
    else ref_clk_toggling<=1'b1;
   end : fvr
end