Assertion :- check the signal is asserted whenever count value exceed to 64

SystemVerilog
,
8

In reply to ben@SystemVerilog.us:

Hi,

I am getting error for below code :-
→ if ((i_ref_clk) == $past(i_ref_clk)) ref_clk_toggling<=1’b0;

property en_fll_1_and_en_sar_0_check ;
 @(posedge i_mon_clk)
 (i_en_fll == 1'b1 && i_en_sar == 1'b0 && !ref_clk_toggling) |=> (o_prog_out_fll == i_prog_trim) ;
endproperty
// ref_clk toggling 
bit ref_clk_toggling;

initial begin 
  repeat(2) @(posedge i_mon_clk); // startup for $past, need 1 clk min  
  forever begin : fvr
    @(posedge i_mon_clk);
******    if ((i_ref_clk) == $past(i_ref_clk)) ref_clk_toggling<=1'b0;
    else ref_clk_toggling<=1'b1;
   end : fvr
end

Error : Clock for sampled value function $past could not be resolved.

→ how it will check whether ref_clk is not toggling ?