Assertion :- check the signal is asserted whenever count value exceed to 64

SystemVerilog
,
7

In reply to rkg_:


property en_fll_1_and_en_sar_0_check ;
 @(posedge mon_clk)
 (en_fll == 1'b1 && en_sar == 1'b0 && !ref_clk_toggling) |=> (prog_out_fll == prog_trim) ;
endproperty
// ref_clk toggling 
bit ref_clk_toggling; 

initial begin 
  repeat(2) @(posedge tosc_clk); // startup for $past, need 1 clk min  
  forever begin : fvr
    @(posedge tosc_clk);
    if (ref_clk) == $past(ref_clk)) ref_clk_toggling<=1'b0;
    else ref_clk_toggling<=1'b1;
   end : fvr
end

Ben SystemVerilog.us