Assertion :- check the signal is asserted whenever count value exceed to 64

SystemVerilog
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6

In reply to harsh pandya:

Thank you Ben and Harsh for quick help :)

One more doubt :
Even when EN_FLL = 1 if the REF_CLK is not toggling then the PROG_OUT_FLL bits should remain same as PROG_TRIM and the block should wait for REF_CLK to start the operation

property en_fll_1_and_en_sar_0_check ;
 @(posedge mon_clk)
 (en_fll == 1'b1 & en_sar == 1'b0) |=> (prog_out_fll == prog_trim) ;
endproperty

But how to take care the REF_CLK toggling or not ?

EN_FLL EN_SAR REF_CLK MON_CLK PROG_OUT_FLL Comments

1 0 Not toggling X PROG_TRIM Even when EN_FLL = 1
if the REF_CLK is
not toggling then
the PROG_OUT_FLL
bits should remain
same as PROG_TRIM
wait for REF_CLK to
start the operation