Assertion :- check the signal is asserted whenever count value exceed to 64

SystemVerilog
,
13

In reply to ben@SystemVerilog.us:

Thank you.

Just to cross check i have changed the property for ap_ref_clk4 below:

ap_ref_clk4: assert property(@(posedge i_ref_clk) ($rose(refclk_en_fll_sync) &&  i_refclk_div == 4'b0010) |=>
                          refclk_output==!$past(refclk_output,8));

But in this case also assertion is getting PASS.

Note :- at posedge of refclk_en_fll_sync, refclk_ouput is getting start toggling ( and before this refclkout_clk is x) :- is it causing problem