Assert signal is stable during certain duration

SystemVerilog
, ,
5

In reply to ben@SystemVerilog.us:

In reply to kernalmode1:
Absolutely yes. Actually, my response should have been

 
($rose(a), v=b) |=> b==v[*0:$] ##1 $fell(a) && b==v; // same as with the until_with

Ben SystemVerilog.us

Hi Ben can i use $stable , and how ?