Assert signal is stable during certain duration

In reply to kernalmode1:

In reply to ben@SystemVerilog.us:
Hi Ben,
Would it be okay to use until_with in this case?

($rose(a), v=b) |=> (b==v until_with $fell(a));

Complementarily,

($fell(a), v=b) |=> (b==v until_with $rose(a));

Absolutely yes. Actually, my response should have been

 
($rose(a), v=b) |=> b==v[*0:$] ##1 $fell(a) && b==v; // same as with the until_with

Ben SystemVerilog.us