Assert signal is stable during certain duration

SystemVerilog
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3

In reply to ben@SystemVerilog.us:

Hi Ben,

Would it be okay to use until_with in this case?

($rose(a), v=b) |=> (b==v until_with $fell(a));

Complementarily,

($fell(a), v=b) |=> (b==v until_with $rose(a));

Thank you for your response.