In reply to bassem yasser:
Assuming signals “a” and “b” are outputs of FFs, this will work:
http://systemverilog.us/vf/test_ab.sv // includes a simple testbench
http://systemverilog.us/vf/test_ab.png // results
property p_ab;
bit v;
($rose(a), v=b) |=> b==v[*0:$] ##1 $fell(a);
endproperty
ap_ab: assert property(@ (posedge clk) p_ab);
// A variation
ap_ab2: assert property(@ (posedge clk)($rose(a), v=b) |=> $past(b)[*0:$] ##1 $fell(a);
Ben Cohen
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October 2013 | Volume 9, Issue 3 | Verification Academy - SVA in a UVM Class-based Environment
SVA in a UVM Class-based Environment | Verification Horizons | Verification Academy