Assert signal is stable during certain duration

In reply to bassem yasser:

Assuming signals “a” and “b” are outputs of FFs, this will work:
http://systemverilog.us/vf/test_ab.sv // includes a simple testbench
http://systemverilog.us/vf/test_ab.png // results


    property p_ab; 
        bit v; 
        ($rose(a), v=b) |=> b==v[*0:$] ##1 $fell(a);        
    endproperty 
    ap_ab: assert property(@ (posedge clk) p_ab);   

// A variation 
   ap_ab2: assert property(@ (posedge clk)($rose(a), v=b) |=> $past(b)[*0:$] ##1 $fell(a);     

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr


  1. VF Horizons:PAPER: SVA Alternative for Complex Assertions | Verification Academy
  2. http://systemverilog.us/vf/SolvingComplexUsersAssertions.pdf
  3. “Using SVA for scoreboarding and TB designs”
    http://systemverilog.us/papers/sva4scoreboarding.pdf
  4. “Assertions Instead of FSMs/logic for Scoreboarding and Verification”
    October 2013 | Volume 9, Issue 3 | Verification Academy
  5. SVA in a UVM Class-based Environment
    SVA in a UVM Class-based Environment | Verification Horizons | Verification Academy