In reply to ben@SystemVerilog.us:
hi Ben, thanks for the reply.
to clarify… currently i’am assuming ‘n’ to be constant value assigned to a register ;this need to be sampled and assert that s1 has to rise n times within event s2.
In reply to ben@SystemVerilog.us:
hi Ben, thanks for the reply.
to clarify… currently i’am assuming ‘n’ to be constant value assigned to a register ;this need to be sampled and assert that s1 has to rise n times within event s2.