In reply to ben@SystemVerilog.us:
Here is a potential solution, assuming “n” is a constant at elaboration time.
import uvm_pkg::*; `include "uvm_macros.svh"
module top;
timeunit 1ns; timeprecision 100ps;
bit clk, a, b, c;
let n=4;
default clocking @(posedge clk); endclocking
initial forever #10 clk=!clk;
// Sig "a" shall change values "n" times between sig "b" and sig "c".
ap_abc: assert property( $rose(b) |-> $changed(a)[=n] intersect c [->1]);
// Sig "a" shall ==1 values "n" times between sig "b" and sig "c".
ap_abc2: assert property( $rose(b) |-> a[=n] intersect c [->1]);
initial begin
repeat(200) begin
@(posedge clk);
if (!randomize(a, b, c) with
{ a dist {1'b1:=1, 1'b0:=2};
b dist {1'b1:=1, 1'b0:=6};
c dist {1'b1:=1, 1'b0:=10};
}) `uvm_error("MYERR", "This is a randomize error")
end
$stop;
end
endmodule
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr
- SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
See Paper: VF Horizons:PAPER: SVA Alternative for Complex Assertions | Verification Academy