APB write cycle assertion

SystemVerilog
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5

In reply to ben@SystemVerilog.us:

Hi Ben,

Thanks for the reply. Yes there are two cases one with wait state and one without wait state.


@(posedge pclk) no_wait_write ##0 // generated by the testbench or slave
              $rose (pwrite && psel) |->  ##1   // 1
              $stable(paddr && pwdata)    ##0   // 2 
              $rose (penable && pready)   ##1   // 3
              pwrite && !psel && !penable);     // 4


$stable(paddr && pwdata) // For this line
Are we not expecting the paddr and pwdata to be stable for 2 clks?