APB write cycle assertion

SystemVerilog
,
2

In reply to rag123:
As you know, I generally use the randomize with weighted probabilities.
It is tricky to get what you need when you have complex scenarios with
stuff like [*2] and $rose and $fell of a combination of signals.
To do that I generally play with the weights, and avoid doing things like


 if (!randomize(..);
 repeat (2) @ (posedge pclk) #1; // <-- avoid 
 if (!randomize(..); 

// *********
// instead, fix your constraints in one shot
 if (!randomize(pwrite,psel,penable,pready) with
         {pwrite dist    {1'b1:=1,1'b0:=1};
          psel dist { 1'b1:=1,1'b0:=1};
          penable dist { 1'b1:=1,1'b0:=1};
          pready dist { 1'b1:=1,1'b0:=1};
         }) `uvm_error("MYERR", "This is a randomize error");
 // repeat (2) @ (posedge pclk) #1;
 if (!randomize(paddr,pwdata)  with
          {paddr  dist {1'b1 :=5, 1'b0:=1};  // Play with the weights
           pwdata dist {1'b1:=5, 1'b0:= 1};})
       `uvm_error("MYERR", "This is a randomize error");

I played with the weights of all the variables and I got failures.
There are too many variables and conditions to get things to work by change thru randomization.
You’ll need to create directed tests, maybe with some randomization.
It’s hard to win the pick-6 lottery!
:)

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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