APB Slave Address range Allocation

UVM
1

Based on the Number of slaves configured ,how to allocate the unique address ranges to each slave ?

Suppose let’s say Number of slaves = 4.
address [7:0]

In this case , slave1 address_range = [1:0];
slave2 address_range = [3:2];
slave3 address_range = [5:4];
slave4 address_range = [7:6];
This is my assumption.

If anything wrong , correct me.

2

Value ranges aren’t first class objects in SystemVerilog, so you can’t create instances of them. You’d have to use a min/max address value pair.

3

Hi Santi,

I assume that by “address ranges” you’re referring to address values not address bits.

If the slaves have equal address spaces then a common configuration would be this:

  • address range of slave 0: [0…63]
  • address range of slave 1: [64…127]
  • address range of slave 2: [128…191]
  • address range of slave 3: [192…255]

You can quickly identify the selected slave by looking at the last two msb of the address (e.g. if address[7:6] == 2’b10 then slave #2 is selected)

Hope this helps,
Cristi

4

In reply to Tudor Timi:

Thanks Tudor for your inputs.
Can You elaborate , how to slice the address based on the MIN/Max value Pair?

5

In reply to Cristian_Slav:

Thanks Cristian,

But how to make it customized?

Suppose let’s say I have configured number of slaves =8 and address width =16.

Then how to slice address range for each slave?

Regards,
Santi

6

In reply to Santi:

Hi Santi,

The algorithm is very simple. Here is a quick SystemVerilog implementation:

module tb;

   initial begin
      automatic int address_width = 16;

      automatic int number_of_slaves = 8;

      automatic int slave_address_range = (1 << address_width) / number_of_slaves;

      for(int slave_index = 0; slave_index < number_of_slaves; slave_index++ ) begin
         automatic int min_addr = slave_address_range * slave_index;
         automatic int max_addr = min_addr + slave_address_range - 1;
         $display("slave #%0d range is [%0d..%0d]", slave_index, min_addr, max_addr);
      end
   end

endmodule

Just be careful with shifting ‘1’ not to pass the ‘int’ limit.

Cristi

7

In reply to Cristian_Slav:

Thanks Cristian.