In reply to Santi:
Hi Santi,
The algorithm is very simple. Here is a quick SystemVerilog implementation:
module tb;
initial begin
automatic int address_width = 16;
automatic int number_of_slaves = 8;
automatic int slave_address_range = (1 << address_width) / number_of_slaves;
for(int slave_index = 0; slave_index < number_of_slaves; slave_index++ ) begin
automatic int min_addr = slave_address_range * slave_index;
automatic int max_addr = min_addr + slave_address_range - 1;
$display("slave #%0d range is [%0d..%0d]", slave_index, min_addr, max_addr);
end
end
endmodule
Just be careful with shifting ‘1’ not to pass the ‘int’ limit.
Cristi