Any Good resources for learning constraints?

SystemVerilog
,
1

I have been searching for a class or book to learn constraints, but I have not found much yet.
All I can see is in the SV IEEE spec and a few examples here and there scattered in different classes and books.
Why are there many books devoted to SVA, but none on Constraints?
I find it helps me to learn something by going over examples.
Does any of you know of good sources:
Books, a collection (such as interview Qs) of solved constraints, a class that starts above the simple syntax?
If not, how did you learn?

Your help will be appreciated

2

In reply to gkaragatchliev:
The book Step-by-Step Functional Verification with SystemVerilog and OVM
provides a slew of constraint examples. Since the code is under
Copyright 2007-2008 SiMantis Inc.
// All Rights Reserved Worldwide
//
// Licensed under the Apache License, Version 2.0 (the
// “License”); you may not use this file except in
// compliance with the License. You may obtain a copy of
// the License at
//
// Apache License, Version 2.0

I am making this code available to all. It is also in my SVA book.

https://systemverilog.us/vf/simantic.tar

Ben Cohen
Ben@systemverilog.us
Link to the list of papers and books that I wrote, many are now donated.

or Cohen_Links_to_papers_books - Google Docs

Getting started with verification with SystemVerilog

3

In reply to gkaragatchliev: