In reply to gkaragatchliev:
The book Step-by-Step Functional Verification with SystemVerilog and OVM
provides a slew of constraint examples. Since the code is under
Copyright 2007-2008 SiMantis Inc.
// All Rights Reserved Worldwide
//
// Licensed under the Apache License, Version 2.0 (the
// “License”); you may not use this file except in
// compliance with the License. You may obtain a copy of
// the License at
//
// Apache License, Version 2.0
I am making this code available to all. It is also in my SVA book.
https://systemverilog.us/vf/simantic.tar
Ben Cohen
Ben@systemverilog.us
Link to the list of papers and books that I wrote, many are now donated.
or Cohen_Links_to_papers_books - Google Docs
Getting started with verification with SystemVerilog