An empty loop variable with multi dimension of the array not working

SystemVerilog
, ,
1

I am trying to learn foreach iterative constraints. LRM says “An empty loop variable indicates no iteration over that dimension of the array” Also gave 2 examples for reference in LRM

**“foreach( A [ i, j, k ] ) …
foreach( B [ q, r, , s ] ) …
The first foreach causes i to iterate from 0 to 1, j from 0 to 2, and k from 0 to 3. The second foreach
causes q to iterate from 5 to 1, r from 0 to 3, and s from 2 to 1.”
**

I have written simple code for same. Can someone explain what is wrong with it ? I am getting compilation error with all tools on EDA playground.


class array;

  rand int unsigned two_dim[5][5];

  constraint my_ct {
    foreach(two_dim[,j]){
      two_dim[j] > 0;
      two_dim[j] < 20;
      
    }
  }
  function new();
  endfunction

  function print();
    $display("Array :%p",two_dim);
  endfunction
endclass

module multi_array();

  array u_array;
  initial begin
    u_array =  new();
    assert(u_array.randomize());
    u_array.print();
  end
endmodule
2

In reply to Digeshkumar:

Your foreach creates an loop iterator j that goes from 0 to 4, but you are still responsible for selecting single elements from your array. For example, the following would have worked

constraint my_ct {
    foreach(two_dim[,j]){
      two_dim[0][j] > 0;
      two_dim[0][j] < 20;
    }
}
3

In reply to dave_59:

Thank you Dave for your response. It works fine with that modification.