An empty loop variable with multi dimension of the array not working

SystemVerilog
, ,
2

In reply to Digeshkumar:

Your foreach creates an loop iterator j that goes from 0 to 4, but you are still responsible for selecting single elements from your array. For example, the following would have worked

constraint my_ct {
    foreach(two_dim[,j]){
      two_dim[0][j] > 0;
      two_dim[0][j] < 20;
    }
}