Ambiguity with Systemverilog Event trigger and @ operator

Hi Team,

I have coded the below example using couple of Systemverilog events. However, I see an ambiguity with the usage. Can someone please help me to clarify these doubts?

//<><><><><><><><><><><> Code <><><><><><><><><><><><><><>
module ev();
event e1,e2;

initial begin
$display(“@%0d: 1: before trigger”,$time);
->e1;//triggers event 1
@(e2.triggered);
$display(“@%0d: 1: after trigger”, $time);
end

initial begin
$display(“@%0d: 2: before trigger”, $time);
->e2;
@(e1.triggered);
$display(“@%0d: 2: after trigger”, $time);
end
endmodule
//<><><><><><><><><><><><><><><><><><><><><><><><><>

//<><><><><><><><><><><><> Output <><><><><><><><><><><><><>
@0: 1: before trigger
@0: 2: before trigger
@0: 1: after trigger
//<><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>

I have the following queries:

  • I believe that the simulation should have been blocked at the point “@(e1.triggered)” in the 2nd initial thread, but that didn’t happen and simulation completed. Any reasons why did that happen?
  • Another query is, why didn’t display messages from both the “@event” got printed and only the one from 1st initial thread got printed?

In reply to kishan patel:

Do you have a race condition between the execution of the two initial blocks. Also, using the triggered method with an event control @ defeats their purpose to help eliminate races.

See

https://verificationacademy.com/forums/systemverilog/events-construct-sv#reply-40987
https://verificationacademy.com/forums/systemverilog/named-events-0#reply-87980