Named events

SystemVerilog
,
1

I have 1 doubt on the below code:

module test;

   event event1,event2;

   initial
     begin
       $display("@%0t:1:before trigger",$time);
       ->event1;
       @(event2);
       $display("@%0t:1:after trigger",$time);
       #20;
     end

   initial
     begin
       $display("@%0t:2:before trigger",$time);
       ->event2;
       @(event1);
       $display("@%0t:2:after trigger",$time);
       #20;
     end
endmodule

Observation:
@0:1:before trigger
@0:2:before trigger
@0:1:after trigger

It doesn’t print the following:
@0:2:after trigger

Please explain the same.

2

In reply to sush:
Please use code tags making your code easier to read. I have added them for you.

The problem here is that you have a race condition and event triggers are not persistent. An event trigger ->ev has to happen before reaching the event control @ev. If the first initial block started executing first, then event1 gets triggered before the second initial block gets suspended waiting for it. But there’s no guaranteed order for executing initial blocks.