Verification Academy
Alternative for disable_iff (rst_n==0) in assert proprty
SystemVerilog
assertion-errors
,
vcs
,
Lint
,
SystemVerilog
,
assertion
,
SVA-Assertion
tejaswig
October 25, 2016, 2:40pm
3
In reply to
ben@SystemVerilog.us
:
thanks for your response!
show post in topic