In reply to tejaswig:
This forum does not discuss tools. However, looking at 1800, your code is correct.
property_declaration ::=
property property_identifier [ ( [ property_port_list ] ) ] ;
{ assertion_variable_declaration }
property_statement_spec
endproperty [ : property_identifier ]
property_statement_spec ::=
[ clocking_event ]
[ disable iff ( expression_or_dist ) ]
property_statement
Thus, the following code looks OK:
module top;
bit clk, rst_n=1;
logic[15:0] i, valid, re;
default clocking @(posedge clk); endclocking
initial forever #10 clk=!clk;
property valid_check;
@(posedge clk)
disable iff (!rst_n) (re[i] |=> valid[i-1]);
endproperty
ap: assert property(valid_check);
endmodule
I suggest that you contact your tool vendor support.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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