Adapter class definition in UVM RAL

UVM
,
1

My Transaction class definition is as below.


class cmd_xtn extends uvm_sequence_item;
	`uvm_object_utils(cmd_xtn)

	   // the  below 9 are the valid commands (cmd)
		/*  parameter LDA  = 4'b0000, // loading the register A with some data
			      LDB  = 4'b0001, // loading the register B with some data
			      OUTA = 4'b0010, // places the contents of Register A on the output bus
			      MVBA = 4'b0011, // copies the contents of Register B into A.
			      MVFA = 4'b0100, // copies the contents of Flag register to Register A
			      ADD  = 4'b0101, // add the contents of A and B and puts the result in Reg A 
			      SUB  = 4'b0110,
			      AND  = 4'b0111,
			      OR   = 4'b1000,
		              LDMR = 4'b1001; // Load the mode register with some data.					*/
						
	/*	Addresses of my registers are 	    reg_A ---> 8'h00
		                                    reg_B ---> 8'h01
						 mode_reg ---> 8'h02
						 flag_reg ---> 8'h03                  	*/
						
	rand bit [3:0] cmd;
	rand bit [3:0] data;
	rand bit rst;
	
	static int no_of_xtns;

	constraint valid_cmd {cmd inside {[0:9]};}
	constraint reset {rst dist {1:=10, 0:=90};}	
	constraint mode_reg {if(cmd == 9)
				data inside {[0:1]};
   			     else
				data inside {[0:15]};}

extern function new(string name = "cmd_xtn");
extern function void disp();
extern function void post_randomize();

endclass

So, there is no specific address field in my transaction class.
And some commands like MVBA and MVFA will read from one register and write into another register. So, how to define adapter class (reg2bus & bus2reg methods) for this kind of transaction?

2

In reply to puttasatish:

If you don’t have an address can you please explain how do you write certain data to your Registers? The command is only defining some operations on your registers.

3

In reply to chr_sue:

Each operation (cmd) is going to work with a specific register.

Example : LDA command is going to write data into Register A
LDB command is going to write data into Register B

4

In reply to puttasatish:

But your Limitation is you can load data to your Registers only via parameters. This is a hard limitation.
My understanding is you hae a processor design with a few instructions. For this you do not Need any geister model in your UVM testbench.

5

In reply to chr_sue:

@chr: Thanks for your reply.

So far, My understanding was “Reg Model can be used to easily access the Registers and memories in the DUT. My design (as you said, it is a simple processor) has got few regitsers like A, B, flag register and mode register”. Hence, I thought of using Reg Model for accessing the registers inmy DUT.

So, can you summarize, where reg_model can be used?

6

In reply to puttasatish:

The UVM reg model approach implements a mirror of your registers in your testbench and provides mechanism to hold both reg models synchronous.
If you need any value from your reg model in your testbench you can directly access the reg model there without running bus cycles. This shortens the access time.
But this is only useful if you have certain amount of registers and these registers are holding values about the status of your design.
In your design you are using your registers to perform your instructions.