Is their any rules for activation and inactive of assertion.
Some times it gets active and never inactive even if the assertion ens and the pass count is only 1.
Some times it never gets active if even if the antecedent pass.
In reply to CHITTARANJAN PATRA:
I explain in my SVA Handbook 4th Edition the Assertion states and the outcomes, This link provides the 4 pages about this topic, it represents important concepts.
I also recommend that you read my paper Understanding the SVA Engine,
Verification Horizons - July 2020 | Verification Academy
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
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- Free books: Component Design by Example FREE BOOK: Component Design by Example … A Step-by-Step Process Using VHDL with UART as Vehicle | Verification Academy
Real Chip Design and Verification Using Verilog and VHDL($3) Amazon.com - Papers:
- SVA Alternative for Complex Assertions
Verification Horizons - March 2018 Issue | Verification Academy - SVA in a UVM Class-based Environment
SVA in a UVM Class-based Environment | Verification Horizons | Verification Academy - Understanding the SVA Engine,
Verification Horizons - July 2020 | Verification Academy