ACK goes high for 1 clk ONLY after 10 cycle of Req going high but never before 10 cycles

SystemVerilog
, , , ,
8

In reply to SVA_USR:

Hi

Try this snippet for all three checks

`timescale 1ns/1ps
module assert_tb;

reg req;
reg ack;
bit clk = 0;
int xyz = 10; 

initial
begin
  forever
  #0.5 clk = ~clk;
end

initial
begin
  req = 0;
  ack = 0;
  // FAIL CRITERIA
  #1  req = 1;
  #9  ack = 1;
  #1  ack = 0;
  // PASS CRITERIA
  #1  req = 0;
  #1  req = 1;
  #10 ack = 1;
  #1  ack = 0;
  #20;
$finish;
end

property assert_check_loop;
int v;
@(posedge clk) 
($rose(req), v=xyz, $display("Assertion Started %t",$time)) |-> (v>0 && !ack, v=v-1)[*0:$] ##0 v==0 ##1 ack ##1 !ack;
endproperty : assert_check_loop 

assert property( assert_check_loop)
$info("PASS");
else
$error("FAIL");

endmodule