ACK goes high for 1 clk ONLY after 10 cycle of Req going high but never before 10 cycles

SystemVerilog
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7

In reply to Srini @ CVCblr.com:

In reply to SVA_USR:
How about?


// Req goes High, after 10 cycle ACK should go high for 1 clk cycle.
// Check : 1. Above condition 2. ACK doesnt get asserted before 10 clk 
// 3. it remains high for 1 clk 
property p1_2_3;
$rose(req) |-> !ack [*9] ##1 ack ##1 !ack;
endproperty : p1

Thanks Srini. It looks perfect but when it comes to Variable delay and not a Fixed constant-10, is where I am stuck.

int xyz=10; //variable coming from an equation and not a constant
property assert_check_loop;
int v;
@(posedge clk) disable iff(disable_assertion)
($rose(m), v=xyz+1, $display(“2: Assertion Started %t”,time)) |-> (v>0, v=v-1'b1)[*0:] ##0 v==0 ##0 $rose(n);
endproperty : assert_check_loop

Here I wanted to use **!n in conjunction with the repeat util operator[*0:]**. something like: (v>0, v=v-1'b1,!n )[*0:]

@(posedge clk) disable iff(disable_assertion)
($rose(m), v=xyz+1, $display("2: Assertion Started %t",$time)) |-> |->(v>0, v=v-1'b1,!n )[*0:$] ##0 v==0 ##0 $rose(n);

As expected, It didnt work :(

Can you please throw some light here.