ACK goes high for 1 clk ONLY after 10 cycle of Req going high but never before 10 cycles

SystemVerilog
, , , ,
6

In reply to SVA_USR:

How about?


// Req goes High, after 10 cycle ACK should go high for 1 clk cycle.
// Check : 1. Above condition 2. ACK doesnt get asserted before 10 clk 
// 3. it remains high for 1 clk 
 
  property p1_2_3;
    $rose(req) |-> !ack [*9] ##1 ack ##1 !ack;
  endproperty : p1

Srini
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