ACK goes high for 1 clk ONLY after 10 cycle of Req going high but never before 10 cycles

SystemVerilog
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4

In reply to vdangeti:

Thanks vdangeti for the reply.
“For Check_2: use $rose (n) |-> ( $past(m,10));”
Observation: The assertion only triggered once. Even though Rose(n) appeared later in simulation, the Assertion remained in Finished state forever after once triggering.
Query: as I mentioned “10” is not fixed and hence I took “xyz”. So 10 cant be used directly in $past(m,10) at the same time being a variable it cannot be used either. Any solution?

Cheers.