ACK goes high for 1 clk ONLY after 10 cycle of Req going high but never before 10 cycles

SystemVerilog
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3

In reply to SVA_USR:

As I suggested in another thread here, split them to multiple - it is easy to maintain. debug and formal friendly.


// Req goes High, after 10 cycle ACK should go high for 1 clk cycle.
// Check : 1. Above condition 2. ACK doesnt get asserted before 10 clk 
// 3. it remains high for 1 clk 

  property p1;
    $rose(req) |-> ##10 $rose(ack);
  endproperty : p1

  property p2;
    $rose(req) |-> !ack [*9];
  endproperty : p2

  property p3;
    $rose(req) |-> ##11 !ack;
  endproperty : p3

Regards
Srini
www.go2uvm.org