ACK goes high for 1 clk ONLY after 10 cycle of Req going high but never before 10 cycles

SystemVerilog
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2

In reply to SVA_USR:

Hi,
For Check_1: $rose(m) |-> ##10 $rose(n) ##1 $fell(n);
For Check_2: use $rose (n) |-> ( $past(m,10));
for Check_3: use $rose and $fell
($rose(m), v=xyz+1, $display(“2: Assertion Started %t”,time)) |-> (v>0, v=v-1'b1)[*0:] ##0 v==0 ##0 $rose(n) ##1 $fell(n) ;