About resetting the TB in UVM

Hello,

I am an intern at Einfochips pvt. ltd. company.
I am currently developing an Ethernet-MAC VIP in my final project.

I have one question regarding reset.

Now, firstly, What I understand that clock and reset will be global signals in interface.
declared such as, interface intf( input logic gtx_clk, resetn );

In this case, I can’t drive reset in other components except top.
so, my question is that what I have understood regarding reset port declaration inside interface as shown above is correct or not ?
and if not then reset will be declared inside interface like this ?
such as,
interface intf( input logic gtx_clk );
logic resetn;
endinterface : intf

In reply to Jaydip_Solanki:

What you should do is create a reset agent/interface/sequence that drives the input to the rest of your VIP interface.

https://verificationacademy.com/forums/uvm/how-deal-initial-reset-dut-use-reset-phase-or-sequence#reply-38892