I want to finish resetting my DUT before allowing my driver and monitor to start their work. Can someone show me how you could use reset phase or sequence? Sequence is prefered because UVM cookbook said the reset phase may not exist in the future UVM release.
begin
reset = 1’b1;
repeat (10) @ (posedge clk); // Hold Reset for 10 clocks for DUT’s power up configuration.
reset = 1’b0; // Release DUT from its reset state.
end
One suggestion would be to have a separate agent control the reset signal, and use a virtual sequence to send a reset_sequence first followed by your other sequences.
virtual sequence will have both reset and normal sequences. How will order of the sequence be controlled? I like reset sequence to go first before normal sequence. How will monitor in agent_o avoid checking any RTL output activities until the reset sequence be completed?
I have this specific requirement in the below code.
task normal_seq::body();
begin
reset_seq.start(null,this); // reset sequence
begin
normal_seq1.start(null,this); // sequences following reset sequence.
normal_seq2.start(null,this);
normal_seq3.start(null,this);
normal_seq4.start(null,this);
normal_seq5.start(null,this);
end
end
endtask
I wanted to have multiple resets during simulation with random delays. and if reset is detected, then normal_seq1 should start executing after each reset.
task normal_seq::body();
fork
repeat(5) begin
#($urandom_range(25,20))
reset_seq.start(null,this); // reset sequence
end
begin
normal_seq1.start(null,this); // sequences following reset sequence.
normal_seq2.start(null,this);
normal_seq3.start(null,this);
normal_seq4.start(null,this);
normal_seq5.start(null,this);
end
end
endtask
Problem is i am not finding a way to return my normal sequence flow to normal_seq1 each time reset is detected. Could you please suggest a way to do it.