A SVA question about how to check a signal will be asserted or de-asserted within a particular timing?

SystemVerilog
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5

In reply to ben@SystemVerilog.us:

Hi Ben,

I have a similar scenario where I want a signal named ‘b’ to be asserted within some time ‘t’ after a signal ‘a’ is asserted. But for my case, the time ‘t’ is variable. I have coded an assertion property like this.


assert property(clk,a,b,t)
@(posedge clk)
    $rose(a) |-> ##[1:t] $rose(b);
endproperty

But I am getting the following error:
Error-Illegal use of non-constant expression
The use of a non-constant expression is not allowed in properties, sequences
and assertions for cases such as delay and repetition ranges.
Please replace the offending expression by an elaboration-time constant

Can you please help me out?

Thanks,
Rajesh