In reply to caowangyang:
but what about if the A/B wasn’t not synchronous to the clk ?
Then you would need to latch those signals. My initial solution for the reset was to have the assertion reset those latches as shown below. But there are issues here because the latch would set it back if A is not set to 0 prior to the the reset by the assertion. Perhaps an external signal or other logic an do the reset. Anyway, this solution, though problematic, can inspire you at finding something that meets your needs.
import uvm_pkg::*;
`include "uvm_macros.svh"
module masync;
timeunit 1ns; timeprecision 100ps;
bit clk; // system clock
bit clk1ns; // the 1 ns clock
bit A, B, AL, BL;
function void resetAL();
AL=0;
endfunction
function void resetBL() ;
BL=0;
endfunction
initial forever #0.5 clk1ns=!clk1ns;
initial forever #5 clk=!clk;
always_latch begin
if(A) AL=A;
if(B) BL=B;
end
// signal B should be deasserted from 1 to 0 within 60ns after signal A asserted.
// Assuming that A is clocked with the clk.
// THIS SOLUTION HAS ISSUES, see comment above.
ap_AB: assert property(@(posedge clk) // posedge clk is leading clocking event
($rose(AL), resetAL()) |-> @ (posedge clk1ns) ##[1:60] ($fell(BL), resetBL()) );
initial begin
repeat(2) @(posedge clk);
@(posedge clk) begin
A <= 1'b1;
B <= 1'b1;
end
repeat(30) @(posedge clk1ns);
B<= 1'b0;
repeat(30) @(posedge clk1ns);
$finish;
end
endmodule
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
- SystemVerilog Assertions Handbook 3rd Edition, 2013 ISBN 878-0-9705394-3-6
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115