A SVA question about how to check a signal will be asserted or de-asserted within a particular timing?

SystemVerilog
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3

In reply to ben@SystemVerilog.us:

Hi, Ben

Sorry for the late response.

I actually thought about the implementation as you wrote, but what about if the A/B wasn’t not synchronous to the clk ? Which means we probably will miss the event $rose(A) since we only validate the assertion in @posedge clk …

Please feel free to correct me if I was wrong somewhere .

Thanks so much,

WangYang