Every assertion needs a leading clocking event to start the evaluation. Also, every variable needs to be sampled by an event. If your timing resolution is 1ns, you’ll need to create a 1ns clock.
import uvm_pkg::*;
`include "uvm_macros.svh"
module m;
timeunit 1ns; timeprecision 100ps;
bit clk; // system clock
bit clk1ns; // the 1 ns clock
initial forever #0.5 clk1ns=!clk1ns;
initial forever #5 clk=!clk;
bit A, B;
// signal B should be deasserted from 1 to 0 within 60ns after signal A asserted.
// Assuming that A is clocked with the clk.
ap_AB: assert property(@(posedge clk) // posedge clk is leading clocking event
$rose(A) |-> @ (posedge clk1ns) ##[1:60] $fell(B) );
initial begin
repeat(2) @(posedge clk);
@(posedge clk) begin
A <= 1'b1;
B <= 1'b1;
end
repeat(30) @(posedge clk1ns);
B<= 1'b0;
repeat(30) @(posedge clk1ns);
$finish;
end
endmodule
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
- SystemVerilog Assertions Handbook 3rd Edition, 2013 ISBN 878-0-9705394-3-6
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115