In reply to caowangyang:
The following code includes a concurrent assertion; I also maintained the original model within the initial. You could also instantiate the concurrent assertion within an initial statement.
module mtime;
timeunit 1ns; timeprecision 10ps;
bit clk;
realtime t_now, low, high, duty_diff_abs, tolerance;
initial forever begin
#10 clk=1'b0;
#9 clk=1'b1;
end
initial begin
tolerance = 1.1ns;
@(posedge clk) t_now=$time; // let clock work for a while
@(negedge clk) high=$time - t_now;
t_now=$time;
@(posedge clk) low =$time - t_now;
duty_diff_abs = (high - low >= 0)? (high - low) : (low - high);
duty_cycle_check : assert(duty_diff_abs <= tolerance);
end
// else $error($psprintf("rise = %0t, fall = %0t, low = %0t,
// high = %0t, duty_diff_abs = %0t, tolerance = %0t", rise, fall, low, high, duty_diff_abs, tolerance));
function realtime ABS (realtime num);
ABS = (num <0) ? -num : num;
endfunction // ABS
property p_time;
realtime v_thi, v_tlo, v_hi, v_lo, v_diff;
@(posedge clk) (1, v_thi=$time) ##0 @(negedge clk) (1, v_tlo=$time, v_hi=v_tlo-v_thi) ##0
@(posedge clk) (1, v_lo=$time-v_tlo, v_diff= ABS(v_hi-v_lo)) ##0 v_diff <= tolerance;
endproperty
ap_time: assert property( p_time);
endmodule
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
- SystemVerilog Assertions Handbook 3rd Edition, 2013 ISBN 878-0-9705394-3-6
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115