In reply to ben@SystemVerilog.us:
Hi Ben,
I think below should work too? eliminating the need for helper code. let me know what you think.
sequence s_req;
rose(req) ##[1:] 1’b1; // endpoints at 0,1,2,… cycles after req
endsequence
grant : assert property (
@(posedge clk)
$rose(gnt) |-> s_req.triggered;
)