In reply to a72:
You need to latch the occurrence of req. Thus,
bit clk, req, grnt, req_occurred, reset_n;
always @(posedge clk) begin
if($sampled(req)) req_occurred <= 1'b1; // updated with the $sampled(
if($sampled(grnt)) req_occurred <= 1'b0;
end
ap_grant: assert property(@(posedge clk) $rose(grnt) |-> req_occurred);
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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