In reply to ben@SystemVerilog.us:
Hi Ben,
Your code looks perfect but here, user needs to take care toggling of “t1.w” each time after calling randomization. So I teaked your code and modified as below. Please let me know if below code has any side effect,
program blk;
class test;
rand bit [2:0] x;
// odd_even bit to indicate whether siganl should be odd or even after randomization
// odd_even == 1 then even data generated
// odd_even == 0 then odd data generated
static bit odd_even;
//pre_randomize function will be called every time before randomize function
function pre_randomize();
$display("Inside pre_randomize");
odd_even = ~odd_even;
endfunction
constraint cons{
(odd_even == 1) -> x%2 == 0;
(odd_even == 0) -> x%2 != 0;
}
endclass : test
initial begin
test t1;
repeat(10) begin
t1 = new();
void'(t1.randomize());
$display ("t1.x = %0d t1.odd_even = %0d", t1.x, t1.odd_even);
end
end
endprogram
@Omran,
Above code will randomize signal in class itself. Please let me know if it works for you.
Regards,
Priyank
Tel: +917939330000 | Cell: 8347036353
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