Why do we need datatypes that are meant to have 4 state values.
All 4 state datatypes are initialized to ‘x’ value in simulation at 0 time. Wouldn’t this cause a lot of trouble rather than being actually helpful.
In reply to natasv:
these are mainly to model the actual hardware behavior. For example, on power-on the content of the RAM is unknown, each bit can be zero/one, which is represented by “X”.
In reply to natasv:
The Z state is used for modeling a number situations where there are multiple drivers on a single net. If a driver has a Z state, that allows another driver to drive a 0 or 1. This is typically how bi-directional busses work.
As you realize, 4-state register variables initialize to X at time 0. Normally a reset signal will take a register from the X state to a 0 or 1, but adding a reset signal to every register can be costly in terms of space and power. So a design tries to limit registers with reset signals to what is absolutely necessary. Dynamic simulation can be used make sure registers come out of the X state. But since Verilog handles X propagation rather poorly, you a right that it can sometime be more troublesome than helpful. This is one are static formal analysis does very well to exhaustively prove that a register gets out of the X state and stays out of the X state.
In reply to dave_59:
Thank you, Dave.
Could you please help explaining how verilog handles ‘x’ propagation poorly.
In reply to natasv:
The simplest case is if-else statements
if (conditions)
do_this;
else
do_that;
Verilog defines the case when the (condition) is X, it optmistically takes the false branch do_that.
The result of adding the values 16’h1040 + 16’b000x is pessimisticly 16’hxxxx.
Some tools have added functionality that treats these cases more realistically by executing all the alternatives and comparing the results of each branch and only setting variables to Xs when there are differences. But this degrades performance significantly as these cases start nesting.
But some cases can only be solved with symbolic or formal analysis. One case is reconvergent fanout of an X value. For example you can reset a register by subtracting it from itself. That will never work in dynamic simulation because X-X is always X. Since there is only one X state, there is no way to know that the 2 X’s are the same value.