In reply to natasv:
The Z state is used for modeling a number situations where there are multiple drivers on a single net. If a driver has a Z state, that allows another driver to drive a 0 or 1. This is typically how bi-directional busses work.
As you realize, 4-state register variables initialize to X at time 0. Normally a reset signal will take a register from the X state to a 0 or 1, but adding a reset signal to every register can be costly in terms of space and power. So a design tries to limit registers with reset signals to what is absolutely necessary. Dynamic simulation can be used make sure registers come out of the X state. But since Verilog handles X propagation rather poorly, you a right that it can sometime be more troublesome than helpful. This is one are static formal analysis does very well to exhaustively prove that a register gets out of the X state and stays out of the X state.