1) Why run phase is task based and all other phases are function based? why can't we write all the phases in either task or function? Can anyone explain detail about this? 2) Can we connect multiple driver to a single sequence and vice versa?

UVM
1
  1. Build, connect, … ,final phase, all the phases we will use function except run phase? what is the main reason?
  2. (a) How can we connect multiple drivers to a single sequence?
    (b) How can we connect multiple sequences to a single driver?
    How can we achieve this?

Thanks & Regards,
Giridhar.K

2

In reply to giridhar.ece@gmail.com:

The run_phase is the phase where the sequence items are generated and processed. This requires time. Only tasks can consume time. All the other phases are used to construct, connect the components or to evaluate results (report_phase). These phases do not need to consume time. Theyy are functions.

You do never connect sequences to a driver. You have always pars of sequencers/drivers.
But you can run a sequence of sequences on this sequencer.

3

In reply to chr_sue:

Hi,

Thanks for the reply.
Can we parse the single sequence to the multiple drivers?
and how can we parse multiple sequences values to single driver?

For example, i have a sequence which will generate from [a-z] random values.
i want to send to the driver like, {a, b, c, d} after that any random value.
How can we achieve this?

4

In reply to giridhar.ece@gmail.com:

You can achieve this by defining 2 sequences, one for sending the data in a defined order and the second which randomizes the order.

5

In reply to chr_sue:

“All the other phases are used to construct, connect the components or to evaluate results (report_phase). These phases do not need to consume time. Theyy are functions.”

Task can consume time. And Task can run with out consuming time also.
So why cant we use build, connect … phases by using task? Means by using tasks also we can run with out consuming time.
Why we are using functions?

6

In reply to giridhar.ece@gmail.com:

Using functiona forces you to avoid time-consuming implementationss.
Finally it is a definition.

7

In reply to chr_sue:

Hi,

Sorry, i didn’t get the clear clarification.
It is a definition that’s why we are using the functions in all phases(except run phase)…

“A function will carry out its required duty in zero simulation time.”
“Tasks also run with a zero simulation however they can if required be executed in a
non zero simulation time.”

There is no other reason why we can’t use tasks in all other phases?

8

In reply to giridhar.ece@gmail.com:

The objective is to have the dynamic part of the UVM environment completed at runtime zero. If we would use tasks instead of functions for constructing/connecting and checking the UVM environment it could be ready at any time after runtime zero. You would not know when starting when the environment is ready for execution. This would make your life quite complicated.

9

In reply to giridhar.ece@gmail.com:
SystemVerilog has this requirement: tasks can call other tasks and functions, but functions can only call other functions. So when you define a function, you are making a guarantee to the caller of that function that it will not consume time.
The guarantee applies to virtual methods as well. By defining a virtual function in a base class, you are creating a requirement that no override of that method consumes time.

The developers of the UVM (Actually this came from the developers of the AVM, which became the OVM, and then UVM) decided to use functions in the base class for everything but the run phase’s virtual methods to enforce the no time consuming requirement.

Yes, they could have made everything a task and left it to the user to ensure that their tasks did not consume time, but that is an unnecessary freedom that just creates difficult to debug issues later on.

10

In reply to dave_59:

Thanks Dave & Chr_sue.